AI在ADC数字校准中的应用

High-speed pipelined ADCs face critical nonlinear distortion challenges under process-voltage-temperature (PVT) variations in 5G/6G communications, optical systems, and radar signal processing. To overcome traditional calibration methods’ inherent assumption dependency and linear modeling limitations along with neural networks’ black-box instability and hardware inefficiency, we propose a Volterra-informed convolutional neural network (VICNN) for pipelined ADC calibration. VICNN rigorously models pipelined ADC nonlinear distortions using Volterra polynomial, decomposes the first-, second-, and third-order kernels via 1D convolutional networks, and constructs a multichannel dynamic weight fusion structure. By preserving Volterra polynomials’ time-frequency coupling properties, the method resolves parameter explosion through low-rank decomposition and adaptively adjusts the contribution weights of differentorder kernels, thereby accurately capturing amplitude-frequency and phase-frequency nonlinear coupling under high-frequency inputs. Simulations and measurements conducted on a 12-bit 750 MS/s pipelined ADC model and a silicon-proven 12 -bit $750 \mathrm{MS} / \mathrm{s}$ pipelined ADC show improvements in both the signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR). Notably, the SNDR and SFDR of the silicon-proven pipelined ADC improve from 55.62 dB and 62.32 dB to 57.04 dB and 73.40 dB respectively, achieved with only 181 parameters and $\mathbf{1. 1 8}$ MFLOPs.

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This article proposes a neural network (NN)-based calibration framework via quantization code reconstruction to address the critical limitation of multidimensional NNs (MDNNs) in analog-to-digital converter (ADC) calibration, where performance degrades drastically under varying input frequencies or sampling rates. Conventional MDNN methods suffer from distribution shifts caused by dynamic oversampling ratio (OSR) variations, necessitating repeated retraining. Our innovation lies in a data reconstruction mechanism: for lower OSR scenarios, a third-order cascaded integrator-comb (CIC) filter inserts pseudo-data points between quantization code to match the NN’s input dimension. For higher OSR scenarios, cyclic downsampling decomposes the original sequence into parallel subsequences processed independently by the same network. For multitone signals, a reconstruction–calibration–summation flow hierarchically handles spectral components. Implemented on an FPGA and covalidated with a commercial 14-bit/1 GSPS pipeline ADC, the framework demonstrates robust performance without retraining. Experimental results show: bandwidth expansion from 16.3% to 84.7% of the Nyquist bandwidth. SFDR improvement of 13.8–27.7 dB and ENOB gain of 2.3–4.6 bits across 10.3–160.3 MHz inputs. This work enables consistent high-precision ADC calibration in dynamic signal environments, facilitating deployment in complex application scenarios.

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Calibrating ADCs in the absence of ground truth presents a significant challenge for high-precision applications. This paper addresses this issue by introducing a novel two-step approach that combines evolutionary strategy and deep learning techniques. First, we employ covariance matrix adaptation evolution strategy to obtain ground truth signal samples with optimal SFDR values. This serves as a robust foundation for the subsequent calibration process. Second, we propose a new calibration neural network architecture called controlled residual convolutional neural networks. This architecture introduces a controlled residual branch within the network, allowing for more effective learning and calibration. The controlled residual branch is designed to adaptively adjust the network’s focus between the main and residual paths, thereby enhancing its calibration capabilities. Experimental results underscore the efficacy of our proposed method. Specifically, we observed a 29.01dB improvement in SFDR, representing the maximum enhancement relative to previous methods. These results validate the effectiveness of our approach in achieving high-precision ADC calibration without the need for the information of ground truth signals, thereby making it feasible for background calibration.

Recently, the neural network has been applied to calibrate the pipelined analog-to-digital converter (ADC) without prior knowledge. However, gradient-based training methods are prone to stagnation in highly nonlinear circumstances. This paper proposes a neural-network-based ADC calibration approach optimized by an improved particle swarm optimization (PSO) algorithm. A dynamic inertia weight strategy, combining sine and exponential functions, is proposed to enable faster convergence in mid-iterations while maintaining exploration in early and late stages. Additionally, a Cauchy mutation mechanism is introduced to enhance global search and avoid local optima. Comparative evaluation using a 14-bit 1.3GS/s commercial pipelined ADC validates the proposed algorithm's efficacy, improving the SFDR from 71.3dB to 86.76dB at 30MHz input, and 66.90 dB to 77.59dB at 450MHz input. Meanwhile, the algorithm also performs well within the Nyquist frequency range.

This article presents a new artificial neural network (ANN)-based calibration mechanism for analog-to-digital converters (ADCs). The proposed mechanism applies ANN to realize the bijective vector recovery mapping (VRM) for nonlinearity calibration and thus effectively suppresses both harmonic distortions and spurs. A new ANN-based calibrator is designed to calibrate both single-channel nonlinearity and interchannel mismatches and significantly improve the performance of ADCs. Through signal-fitting-based training process and noise adding, the proposed mechanism and calibrator can calibrate the general nonlinearity and mismatches of ADCs, including but not limited to the typical nonideality that conventional calibration techniques commonly concern (such as interstage gain error, digital-to-analog converter (DAC) error, and timing mismatch). For verification, an on-chip ANN-based calibrator is implemented in a 12-bit 600-MS/s four-channel time-interleaved (TI) ADC prototype. The measurement results show that signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are improved from 32.79 and 35.30 to 62.45 and 74.21 dB, respectively. Another off-chip ANN-based calibrator is applied to a commercial 12-bit 5.4-GS/s four-channel ADC, and the results show that the SNDR and SFDR are improved from 42.38 and 43.17 to 53.98 and 78.25 dB, respectively.

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This paper presents a 2-stage pipelined-SAR ADC with artificial-neural-network (ANN) based digital calibration algorithm to calibrate the mismatch error in the <inline-formula> <tex-math notation="LaTeX">$1^{\mathrm {st}}$ </tex-math></inline-formula>-stage capacitive DAC (CDAC) and the inter-stage gain error (IGE) together. Previous ANN-based calibration schemes suffer from excessive power and hardware overhead due to the large number of network parameters. To facilitate hardware implementation, the proposed algorithm only requires <inline-formula> <tex-math notation="LaTeX">$N_{1}+1$ </tex-math></inline-formula> input parameters (<inline-formula> <tex-math notation="LaTeX">$N_{1}$ </tex-math></inline-formula> is the resolution of the <inline-formula> <tex-math notation="LaTeX">$1^{\mathrm {st}}$ </tex-math></inline-formula>-stage SAR ADC), in which the overall output of the <inline-formula> <tex-math notation="LaTeX">$2^{\mathrm {nd}}$ </tex-math></inline-formula>-stage SAR ADC is combined into a single parameter. In addition, the ANN utilizes a single-neuron hidden layer with linear activation function to calculate the actual bit weight of the ADC, remarkably reducing the hardware overhead and power consumption of the calibration circuit. The prototype 12-bit, 250 MS/s pipelined-SAR ADC with “loop-unrolled” architecture is implemented in 40-nm CMOS, in which a ring amplifier with improved bias circuit is used to realize a robust closed-loop gain for residue amplification. With the ANN-based calibration circuit implemented in an FPGA, the calibrated ADC achieves the SNDR of 65.0 dB and the SFDR of 84.0 dB at Nyquist input (124 MHz), with a Schreier figure of merit of 169.0 dB and a Walden figure of merit of 14.0 fJ/conv-step. The ADC core consumes 4.95 mW, with an active area of only 0.013 mm2.

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Aiming to address the timing skew mismatch in the time‐interleaved analog‐to‐digital converter (TIADC) system, this paper presents a timing skew mismatch calibration method based on a back propagation (BP) neural network optimized by an adaptive genetic algorithm (AGA). In this paper, a trained BP neural network is used to detect the timing skew mismatch in the TIADC system, and the variable delay line is used to calibrate it. In this paper, AGA is used to optimize the BP neural network, accelerating its training speed and improving the detection accuracy of timing skew mismatch in the system. The proposed approach boasts superior detection speed and accuracy compared to other methods. In this paper, an 18‐bit 1GS/S 4‐channel TIADC system is simulated and the timing skew mismatch in the system is corrected. Simulation results show that the proposed calibration method has fast detection speed, high detection accuracy, and calibration accuracy. After completing the timing skew mismatch correction, the performance of the TIADC system is dramatically improved. The effective number of bits (ENOB) of the system increases by 9.5 bits, and the spurious‐free dynamic range (SFDR) increases by 59.9 dB.

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This brief proposes a neural network-enhanced digital background calibration scheme for calibrating the linear and the third-order nonlinear gain errors of the residue amplifier (RA) in pipelined ADCs. A customized convolutional neural network (CNN) is designed to extract the information of the linear and the third-order nonlinear gain errors of RA with dither injection. Compared to traditional correlation-based calibration algorithms, the proposed method can significantly improve convergence speed and robustness against dither capacitor mismatch. Compared with previous neural network-based calibration techniques which are commonly used for foreground calibration, the proposed method can operate in background to follow error variations without any risk of signal fidelity problems. Off-chip validation with a silicon-proven 14-bit 1.3 GS/s pipelined ADC shows that, after calibration, the SNDR and SFDR are improved from 46.6 dB and 55.2 dB to 63.1 dB and 80.4 dB, respectively. Moreover, the proposed method takes only 75K samples to reach convergence, whereas traditional algorithms require several to hundreds of millions of samples to achieve convergence ( $10{^{{2}}} \sim 10{^{{4}}}$ times faster). The implementation result shows that the power consumption of the proposed calibrator is 34.8 mW at 1.3 GHz clock frequency.

This paper presents an effective digital calibration method based on Volterra neural network (VNN) for pipeline analog-to-digital converters (ADCs). Typically, the nonideality of pipelined ADCs results in dynamic nonlinear systems that are difficult to comprehensively calibrate. The proposed approach combines the strong nonlinear modeling capabilities of Volterra series with the adaptability of neural networks to accurately compensate for nonlinear distortions in pipeline ADCs. The effectiveness of VNN-based calibration is verified in MATLAB and ZYNQ-7000 FPGA. A 625-MS/s 12-bit pipeline ADC in 28 nm CMOS process is presented to verify the proposed calibration technique. The experimental results show that owing to the proposed powerful calibrator, the SFDR and SNDR achieve 79.8 dB and 60.7 dB at low frequencies, 74.3 dB and 59.1 dB at high frequencies, respectively.

This brief proposes a convolutional neural network (CNN)-based calibration method for timing skew in time-interleaved (TI) ADCs. Compared to previous neural network-based methods, this work employs a lightweight network for frequency recognition and then dynamically configures the structure of a subsequent CNN based on the recognition result. By adapting the calibration scheme to the input signal characteristics, the proposed method achieves high accuracy, reduces overfitting at low frequencies, and saves hardware cost. A 12-bit 3.6-GS/s TI-ADC test board with programmable timing skew is used to validate the method. Measurement results show that at Nyquist input, SNDR and SFDR are improved from 34.23 and 35.77 dB to 51.85 and 62.67 dB after calibration, respectively. Implemented on FPGA, the power consumption of the calibrator is 40 mW, where the frequency recognition network contributes 12.5%. The proposed method is applicable to various types of input signals, including single-tone, multi-tone, and modulated signals.

This paper presents a novel parallel convolution-self-attention neural network (PCSANN) based calibration scheme for Pipelined and Pipelined-SAR ADCs. Combining convolution neural network (CNN) and self-attention neural network (SANN), the proposed architecture jointly calibrates various nonlinearities in ADCs as a black box, including comparator offsets, inter-stage gain error (IGE), inter-stage nonlinearity, digital-to-analog converter (DAC) errors, memory effect (ME), etc. This proposed calibration scheme is validated with a fabricated 12-bit 150MSps pipelined ADC prototype and a fabricated 12-bit 750MSps pipelined-SAR ADC prototype. Measurement results show that the spurious-free dynamic range (SFDR) of the pipelined ADC is improved by 14.17dB from 64.98dB to 79.15dB, and the pipelined-SAR ADC achieves a 7.60dB improvement in SFDR from 63.00dB to 70.60dB.

This paper presents a convolutional neural network (CNN) based error calibration scheme for pipelined ADC. The output of the pipelined ADC is taken as the input data of the network, and the network produces error compensation values. The network is applied in a 14-bit 1GSps pipelined ADC model with nonlinear errors including inter-stage gain error (IGE), DAC errors, thermal noise and sampling jitter for verification. The trained network scheme is verified with various types of signals including single-tone, dual-tone, amplitude modulation (AM) and frequency modulation (FM) signals. Simulation results show that, the SFDR and SNDR of the pipelined ADC are improved from 62.58dB and 58.82dB to 89.86dB and 66.66dB after calibration. Meanwhile, after calibration, the spurs of the dual-tone, AM and FM signals have been effectively suppressed.

This brief proposes a novel calibration method for analog to digital converters (ADCs) based on neural network (NN). In the proposed algorithm, NN is designed to realize the inverse mapping of the non-ideal transfer function of the ADC. An experiment-based spectrum model (EBSM) is established based on the harmonic distortions and spurs caused by non-ideal factors in ADCs. The NN is trained and evaluated with EBSM, and harmonic distortions and spurs be suppressed. The proposed calibration method demonstrates strong portability and can be applied to the calibration of multiple errors in both single-channel and multi-channel ADCs. The calibrator is implemented in Xilinx Virtex-7 FPGA and applied to the online calibration of a 12-bit 150 MS/s pipelined ADC and a 12-bit 600 MS/s time-interleaved ADC. Measurement results indicate that after calibration, the SFDR has improved from 65.85 dB to 82.29 dB, respectively.

This paper introduces an algorithm for improving the accuracy of the ADC acquisition system based on pruning neural network, which can calibrate the errors caused by the analog-to-digital conversion module and other parts in the acquisition system, and effectively improve the accuracy of the ADC acquisition system. By using techniques such as neuron pruning, weight clustering, and parameter quantization, the network we trained greatly reduces hardware resource consumption while achieving the calibration effect of a fully connected neural network. It enables this network easier to deploy in embedded systems. The simulation results show that in the case of a signal input close to the Nyquist frequency, for a 12- bit 12.5MS/s ADC acquisition system, the ENOB can be increased from 5.31 to 8.83, and the SFDR can be increased from 46.3dB to 66.4dB.

This paper proposes a background calibration algorithm based on neural network (NN) for bandwidth mismatch in TI-ADCs. The calibration method uses a three-layer neural network to achieve lower training resource consumption and higher calibration accuracy by processing the input and target output data of the TI-ADC. The optimal structure of the neural network is determined by simulation. A 12-bit, 3.2GS/s TI-ADC model is used to validate our proposed method. Simulation results show that SNDR and SFDR are improved from 49.75dB and 53.37dB to 69.51dB and 88.75dB after calibration, respectively. The calibration method provides good calibration performance for different types of signals, including single-tone and multi-tone signals, and it is applicable over a wide frequency range. Meanwhile, it has a high effective bandwidth that covers the overall Nyquist frequency range.

The article proposes a neural network-based digital calibration improvement method for ADC, targeting the problems of large network size and computation complexity in neural network-based ADC digital calibration. The proposed method involves three aspects: changing the neural network output value to be fitted, optimizing gradient descent with a simulated annealing algorithm, and using half-precision parameters. Improvements 1 and 2 slightly increase the algorithm complexity, while improvement 3 reduces the multiplier area and power consumption. Experimental results show that Improvement 1 significantly reduces the required number of training iterations for convergence, Improvement 2 improves the stability of neural network training, and Improvement 3 does not significantly degrade algorithm performance. The proposed method has low implementation complexity and can provide guidance for optimizing neural network digital calibration circuits on chips or FPGAs.

In this paper we introduce an area efficient time-interleaved charge-injection-cell SAR ADC. The prototype TI-ADC interleaves 8 CIC SAR channels for a sampling rate of 6Gs/s and a compact area of 0.0060Smm2. A neural network calibration algorithm corrects multiple error sources in the time-interleaved ADC. The neural calibration method effectively improves the average measured ENOB of the TI-ADC from 4.1 bits to 5.49 bits.

This paper demonstrates a new neural-network-based calibration technique for inter-channel mismatches of time-interleaved ADCs. By providing with signal value and derivative value of each channel, the network could calibrate the gain mismatch, offset mismatch, and timing mismatch of TI-ADCs. By utilizing signal feature fitting, the ground truth for network training could be obtained without an accurate reference ADC nor a precise ADC error model. Simulation results show that the proposed calibration technique can increase the SFDR of a 14-bit 4Gsps TI-ADC from 32.77 dB to 91.71 dB for single-tone signals, and suppress the maximum spur from −48.51 dBFS to −101.23 dBFS for multi-tone signals. A hardware implementation resources estimation is also given in this paper.

This paper proposes a background calibration scheme for the pipelined‐Successive Approximation Register (SAR) Analog‐to‐Digital Converter (ADC) based on the neural network. Due to the non‐linear function fitting capability of the neural network, the linearity of the ADC is improved effectively. However, the hardware complexity of the neural network limits its application and promotion in ADC calibration. Hence, this paper also presents the optimization schemes, including the neuron‐based sharing neural network and the partially binarized with fixed neural network, in terms of calibration architecture and algorithm. A 60 MS/s 14‐bit pipelined‐SAR ADC prototyped in 28‐nm technology is utilized to verify the feasibility of the proposed calibration method. The measurement results show that the proposed calibration greatly enhances the Spurious Free Dynamic Range (SFDR) and Signal‐to‐Noise‐and‐Distortion Ratio (SNDR) from low frequency to Nyquist frequency. Meanwhile, the original calibrator and improved calibrator are synthesized in Synopsys Design Compiler to compare their hardware complexity. Compared with the unoptimized version, the optimized schemes can decrease the logic area and the network weights up to 76% and 52%, with negligible loss in calibration performance.

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This paper presents a neural network-based digital calibration algorithm for high-speed and time-interleaved (TI) ADCs. In contrast with prior methods, the proposed work features joint amplitude-dependent and phase-dependent nonlinear distortion correction without prior-knowledge of ADC architecture feature. A dynamic calibration is first used to compensate for phase-dependent distortion. Two training optimizations, including a sub-range-sample-based batch schemes and a recursive foreground co-calibration flow are proposed to reduce the error and overfitting and further save hardware resources. A practical calibration engine is also investigated for interleaved ADCs with distributed weight and shared weight methods. To demonstrate the effectiveness of the method, the calibration engine is verified by two fabricated ADC prototypes, a 5 GS/s 16-way interleaved ADC and a 625 MS/s interleaving-SAR assisted pipeline ADC. Measurement results show that SFDR is improved between 16.9dB and 36.4dB before and after calibration for different frequency inputs. To trade-off between accuracy and power consumption, a quantized and pruned engine is implemented on both FPGA and 28nm CMOS technology. Experimental results show that the dedicated calibration on silicon consumes 8.64mW with 0.9V power supply at 333MHz clock rate. Measurement results show that the quantized hardware implementation has only 0.4-4 dB loss in SFDR.

This work introduces a Memory-Aware Gray-Box Neural Network (MAGB-NN) for Analog-to-Digital Converter (ADC) calibration. Three key techniques are utilized to simultaneously ensure high efficiency and low hardware cost. First, the ADC is treated as a gray-box system, where prior knowledge of ADC characteristics is utilized to optimize input-layer weights, thereby reducing both network complexity and convergence time. Second, a recurrent layer is incorporated to retain prior information, enabling compensation for memory effects in high-speed ADC operation. Third, replacing multipliers with multiplexers in the output layer significantly reduces hardware overhead. A 14-bit 2.6GS/s pipeliend ADC and a 14-bit 60MS/s split pipeliend-SAR ADC are utilized to verify the proposed calibration algorithm. This approach exhibits an improvement of over 13 dB in Spurious-Free Dynamic Range (SFDR) of both ADCs. The hardware feasibility of the algorithm is verified by the FPGA and TSMC 28nm process. The experimental results show that the proposed ADC calibrator only has an area of $ 50600~{\mu }$ m2 and only consumes 7.86 mW at 1 GHz clock rate.

An analog background calibration approach is presented for the full calibration of pipeline analog‐to‐digital converters (ADCs). A well‐trained neural network acts close to the ideal 1.5‐bit stage, and its residue is compared with the real 1.5‐bit stage including gain error and amplifier nonlinearities. The detected error is used to compensate for the imperfect residue using four calibration polynomial coefficients. The corrected residue enters the second stage of the pipeline ADC and follows a normal path to achieve high resolution. The introduced structure is verified in a 12‐bit pipelined ADC composed of 11 stages; the first 10 stages have a 1.5‐bit structure, while the last stage is a 2‐bit flash. The sampling frequency is 100 MHz, and 10% non‐ideal factors (5% for each of the nonlinear and gain errors and 10% for the aggregated error) are considered for the first stage, while the input is 19.5 MHz sinusoidal waveform. A random noise is applied to the input to limit the effective number of bits (ENOB) to almost 11.8. The evaluation parameters of the ADC are extracted, signal‐to‐noise and distortion ratio increases from 39.14 to 72.91 dB, spurious free dynamic range improves from 40.94 to 79.69 dB, and the ENOB enhances from 6.2 to 11.82. The presented mechanism shows an acceptable accuracy in the high‐speed and high‐resolution ADCs.

Future energy-harvesting (EH) brain-machine interfaces (BMI) present fundamental design challenges to analog-to-digital converters (ADC) for neural signal digitisation and recording. Ultra-low power (ULP) consumption, maximised area density, bandwidth and dynamic range as well as amenability to ultra-low voltage (ULV) supply are all desirable performance specifications. This article presents a digitally intensive openloop voltage-controlled-oscillator (VCO)-based ADC operating at an ULV supply of only 0.2V in 28nm CMOS. We introduce a novel design framework harnessing the spatio-temporal dynamics of coupled oscillator ensembles (COE) for open-loop voltage-to-frequency (V -to-f) analog linearisation, as applied to high impedance input transconductor-driven VCOs. A machine learning (ML)-driven foreground calibration engine employing gradient descent automatically optimises the integrated digitally programmable ‘tuning knobs’ of the COE network to guide its self-adaptive linearisation. A Verilog-A calibration engine integrated with the transistor level COE was developed to perform full-system transient simulations (lasting several miliseconds) which reduced the dominant third-order harmonic distortion (HD3) from −35dBc to −70dBc for a near rail-to-rail differential input voltage swing of ±180mV, verifying the calibration process.

Recently, the neural network has been applied to calibrate the successive-approximation-register and pipelined analog-to-digital converters (SAR-Pipelined ADCs), which requires no prior knowledge. However, the large hardware area of the full-precision neural network (FPNN) limits the promotion of this method. This paper proposes an optimization scheme called partially binarized and fixed neural network (PBFNN) to simplify the hardware through the following mechanisms. First, the multipliers that occupy a considerable area are optimized by binarization. Second, the fixed layer does not require training, hence saving the hardware for backpropagation. A 14-bit 60 MS/s ADC prototyped in 28-nm CMOS process is used to verify the PBFNN-based calibration. The measurement results show that the ADC achieves an SFDR of 95.0 dB and an ENOB of 10.6 bit. Compared with the previous scheme, the SFDR and ENOB are lossless. We also synthesize both schemes in Synopsys Design Compiler with a 28-nm library. The synthesis result indicates that the hardware area is optimized by 71.95%.

Abstract A new digital background calibration scheme for non-linearity of successive approximation register (SAR) analog-to-digital convertor (ADC) is presented. Since non-linearity of high resolution SAR ADC is mainly caused by the difference between the real and ideal weights of capacitor digital-to-analog convertor (CDAC) with respect to the normalized-full-scale, calibration of weights of more significant bits is necessary when the resolution of SAR ADC comes to more than 12 bits. By using back-propagation algorithm to train the normalized real weight of more significant bits (MSBs) in neural network without any change in SAR ADC circuit design, the calibration table for each bit is implemented and updated in the digital domain without interrupting normal ADC process, which is used to correct the raw SAR code in the background to improve the performance of ADC, which is suitable for some detection applications in particular circumstances. In MATLAB simulation, the signal to noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of a 14-bit with 1-bit redundancy SAR ADC model are improved to 85.59 ​dB and 97.27 ​dB from 56.65 ​dB to 77.07 ​dB using the proposed calibration scheme, at a standard deviation of a unit capacitor of 2%.

This paper proposes a novel high-precision ADC digital calibration algorithm based on neural network (NN). The algorithm is to suppress the harmonic distortion caused by the non-ideal factors in ADC. As a result, regardless of the non-ideal types, it can be universally used as a back-end calibration black box in various ADC structures. A 14-bit ADC with trained NN reaches more than 12.3-bit of ENOB in behavioral simulation. We also applied the NN to a practical 12-bit sigma-delta ADC and achieved a significant improvement of more than 1-bit of ENOB.

Although the calibrator based on neural networks performs well in nonlinearity calibration for SAR-Pipelined ADC, it suffers from considerable hardware complexity. This paper proposes a network structure called layer-based neural network (LSNN) to optimize this calibrator. Compared with the traditional structures, LSNN has the following advantages. First, it optimizes storage and logic simultaneously. Second, it reduces the storage read and write bandwidth by half at least. Third, a simplified computing mechanism that reduces the adders for backpropagation by half can be introduced based on LSNN. A 14-bit 60 MS/s ADC fabricated in 28-nm process is used to verify the feasibility of the proposed structure. The measurements show that the SFDR and SNDR of the ADC calibrated by LSNN increase from 68.3 dB and 44.6 dB to 95.4 dB and 65.4 dB, respectively. Compared with the traditional neural network structures, the LSNN can optimize up to 76.7% of the logic area, 53.2% of the storage and 64.8% of the bandwidth.

A novel background calibration technique for timing mismatch in time-interleaved ADCs (TI ADCs) with fast convergence speed is presented in this brief. The proposed calibration applies a customized neural network (NN) to extract the information of timing skews for compensation. Compared to the conventional background methods for calibrating timing mismatches without reference, this brief significantly increases the convergence speed with high accuracy. In comparison with prior NN-based calibration works, this brief could follow the error changes in the background and has stronger robustness, also without any risk of fidelity problem. A 12-bit 3GSps 4-channel TI ADC model with noise and jitter is simulated for verifying the effectiveness of this technique. Simulation results show that the proposed technique could improve the SNDR and SFDR by 7.41dB and 24.73dB respectively, with only 1536 samples for convergence. Off-chip validation with a 12-bit 3GSps 4-channel TI ADC also proves the effectiveness and practicality of this brief.

This paper presents a novel calibration scheme for single-channel SAR, pipelined and pipelined-SAR ADCs using Kolmogorov-Arnold networks (KANs). In the proposed scheme, a multi-sample KAN (MS-KAN) is designed to realize nonlinear code synthesis (NLCS), achieving effective calibration for general nonlinear errors. The MS-KAN-based calibrator can be converted into an analytical expression, making the calibration process transparent, with stronger interpretability, predictability and reliability compared to previous neural network-based calibration algorithms, and assisting in the analysis of ADC nonidealities. Meanwhile, the proposed scheme achieves high calibration performance with low hardware overhead. The proposed scheme also requires much fewer training samples, thereby reducing the effort required for both chip testing and network training. The MS-KAN-based calibrator is verified with two silicon-proven ADCs, a 14-bit 1.3 GS/s pipelined ADC and a 10-bit 700MS/s SAR ADC. Measurement results show that SFDR is improved by 11.5 dB to 30.9 dB after calibration. The quantized calibrators are implemented on both FPGA and 28nm CMOS technology, where a piecewise polynomial (PWP) method is adopted to simplify the implementation of the calibrator. The post-layout simulation results show that the calibrator for the real-time calibration of the pipelined ADC consumes only 6.32 mW, while the calibrator for the SAR ADC consumes 2.42 mW.

This paper presents a Flash A/D converter to be integrated at the periphery of mixed-signal computing memories for convolutional neural networks. We investigate the feasibility of a true time-multiplexing, which allows to greatly relax the ADC requirements of area and aspect ratio, without sacrificing the data throughput of the memory array. The ADC, based on a strong-arm latched comparator combining built-in reference generation, body bias, and offset calibration, exhibits 29.8-dB SNDR at 3.2 GS/s with 1.5-mW power consumption, and a silicon area of $900\ \mu\mathrm{m}^{2}$. Integrated with the memory array, the converter enables up to 32-to-1 column multiplexing with 20 ns of A/D conversion latency.

This paper designs a pipelined memristive neural network ADCs. Cascade the sub stages of memristive neural network ADC with pipeline structure to improve the conversion accuracy of memristive neural network ADC. First, the signal flow of the pipeline architecture is optimized, and the compatibility between the 4 bit memristive neural network ADC and the pipeline architecture is solved. Secondly, the application of random disturbance circuits in pipeline architecture was analyzed. Combining the calibration circuit with the pipeline DAC to reduce the power consumption of the calibration circuit. Finally, the circuit model of memristive neural network ADC is built and compared with the existing memristive neural network ADC. The results indicate that the pipeline structure ADC designed in this chapter has the advantage of adaptive calibration in terms of calibration function.