class-F VCO

论文利用双环路光电振荡器结构来解决单环结构光电振荡器单模输出与高Q值的矛盾，双环OEO系统由MZM调制器、射频滤波器、偏振分束器、偏振合路器、两段不同长度的单模光纤、光电探测器和射频放大器等器件组成。PBS加PBC的分光合路方案能保证双环中光场的偏振正交性，大大降低了干涉拍频引入的相位噪声。文章中采用两种不同光纤长度仿真实验获得X波段内频率可调谐的高质量微波信号，得到了很好的相位噪声效果。

A novel dual-core dual-mode class-F voltage-controlled oscillator (VCO) with wide frequency tuning range (TR) is proposed in this letter. It consists of two coupled parallel “8”-shaped inductor and two crossed-coupled VCO cores. To increase the TR of the proposed VCO without adding additional footprint size, a single-turn common-mode inductor is embedded inside the “8”-shaped inductor. By controlling the mode switches, the inductor can work in different modes with large inductance difference, realizing large VCO TR consequently. Then, the two coupled inductors were engineered to form the fundamental and third harmonic resonances, respectively, thereby producing a pseudo-square wave output waveform and realizing class-F operation. With the proposed configuration, the phase noise (PN) of the proposed VCO can be significantly reduced without increasing VCO core size. To demonstrate the proposed idea, a VCO prototype is fabricated in a 65-nm CMOS process with a core size of $1.235\times 0.8$ mm. It achieves a wide frequency TR from 2.84 to 7.04 GHz. The measured PN at 1-MHz offset is from −123.9 to −113.1 dBc/Hz, demonstrating an FOMT of 196.0–201.3 dBc/Hz.

This article introduces a compact and low phase noise (PN) 19-GHz quad-core class-F voltage-controlled oscillator (VCO) based on a square-geometry transformer tank using the inductor-sharing technique. The proposed square-geometry transformer tank is inherently more compact than the prevalent topologies such as star geometry, dual-row geometry, and circular geometry. The inductor-sharing technique is introduced to merge neighboring inductors into smaller ones, which further reduces the chip area. Moreover, the proposed quad-core topology supports impedance boosting at harmonic frequencies without extra chip area consumption and class-F operation is adopted to achieve better PN performance. The quad-core VCO prototype is designed and fabricated in a 65-nm CMOS process. Measured performances are 17.6 to 19.4 GHz frequency range with −137.2 dBc/Hz minimum PN at 10 MHz offset from 19 GHz carrier with 46 mW power consumption and 0.9-V supply, resulting a figure of merit (FoM) of 186.1 dBc/Hz. Thanks to the proposed square-geometry and inductor sharing technique, the proposed VCO is the smallest in quad-core VCOs with a similar operating frequency with a core chip area of $0.3\times0.3$ mm2 and the corresponding FoMA is 196.5 dBc/Hz.

The current 5G and future 6G high-speed mobile-Internet era puts forward stricter requirements on the power consumption, silicon area, and phase noise specifications for local oscillators (LOs) in mobile and portable devices, especially in battery-powered mobile phones, notebook computers, and unmanned aerial vehicles (UAVs) used for mobile base stations. Over the past few decades, intensive research to improve the power efficiency of RF and millimeter-wave oscillators while maintaining required phase-noise characteristic has been carried out. As represented in Fig. 8.1.1, the authors in [1] reported a BiCMOS series-resonance VCO with the lowest phase noise among silicon-based oscillators identified in [1] at the cost of high power consumption (600mW), which is not feasible for energy-efficient applications. In addition to the series resonance technique, the commonly used method to reduce the phase noise is to introduce a high resistance at the second harmonic frequency. However, the head filter in [2] that generates the high resistance occupies additional area and cannot prevent noise current injection at the GND. Although separate filters are added at the VDD and GND, as reported in [3], the noise current passing through the head common-mode inductance is coupled in the same phase to the noise current of the bottom inductance, which increases the total injected noise to some extent. To solve the problem of the additional area for the common-mode resonator, the authors in [4] merged the common-mode filter with the differential-mode resonator at the cost of the reduced switching speed of the gate and worsened phase noise and the ability to cut off the noise-injection path from the VDD coupled to the gate. In order to overcome the above-mentioned issues, a 11.5-to-14.3GHz dual-core Class-F VCO with common-mode-noise self-cancellation and isolation technique is proposed in this paper. Without occupying additional area, the injection noise of the VDD and the GND is cancelled inherently at the same time, and the noise path from the drain to gate is isolated. The measurement results indicate that the proposed common-mode-noise self-cancellation and isolation VCO achieves -119.2dBc/Hz phase noise at 1MHz offset from a carrier of 11.8GHz, which translates to an FoM of 192.8dBc/Hz. The reported FoM is competitive among VCOs operating in a nearby frequency range.

This article presents a cryogenic mode-switching class-F voltage-controlled oscillator (VCO) aimed at addressing the demand for wideband, low phase noise (PN) local oscillator signals in cryo-CMOS quantum controllers. First, to resolve the issues of manual alignment of harmonics and resonances, and excessive drain-to-gate gain leading to reliability concerns in transformer (XFMR)-based class-F VCOs, a single-core class-F VCO architecture with harmonic-resonance self-alignment property was constructed by utilizing a symmetrical and XFMR-less dual-mode resonator (DMR), which features a pair of concurrently tunable and fixed-ratio (3:1) resonant frequencies. Since the pseudo-square oscillating voltage waveforms are directly fed back to the gates, a sharper class-F oscillation is achieved to reduce the impulse sensitivity function (ISF) even without the drain-to-gate gain. Then, the lossless mode-switching technique is introduced into two coupled single-core class-F VCOs to extend the frequency tuning range (FTR) and gain about 3-dB PN reduction. The coupling realized by inductive and small magnetic elements does not disrupt the self-alignment characteristics for under mode-switching operation. Large-dimension transistors were employed to design the negative transconductance cells to suppress flicker noise and channel shot noise at cryogenic temperatures (CTs). Furthermore, the worsened nonlinearity in MOSFETs at CTs is exploited to enhance the waveform shape of class-F oscillations. The designed and fabricated VCO prototype achieves 5.3- to 10.6-GHz FTR with a best PN of −153.1 dBc/Hz at 10-MHz offset at 3.7 K, corresponding to a best figure of merit (FoM) and FoM for FTR (FoMT) of 203.8 and 220.3 dBc/Hz, respectively.

The fast-developing 5G communication is setting increasingly stringent requirements for on-chip voltage-controlled oscillators (VCOs). On the one hand, the VCOs need to generate an extreme pure spectrum to support complicated modulations, corresponding to a low phase noise (PN). On the other hand, a wider frequency tuning range (FTR) is preferred for various wideband applications. In addition, the flicker noise up-conversion has become a serious issue worsening PN at low offset frequencies, especially at advanced technology nodes. Practice has been made to improve the PN and FTR performance. The VCO in [1] covers a wide FTR of 80.6% through triple modes using standard VDD However, no harmonic shaping technique is used to improve PN, and it also suffers from the sacrificed tank's Q because of the asymmetry topology. In [2], the author uses circular topology inductors to obtain a high Q for a 22.4-to-26.8GHz VCO. A −138dBc/Hz low PN at 10MHz offset is achieved. However, the common-mode (CM) harmonic manipulation is absent, resulting in a 1.06MHz 1/f3 corner frequency. Nevertheless, a tail-less NMOS-only structure may face reliability issues under standard VDD The VCO in [3] reaches low PN with low 1/f3 corner frequencies using 2nd harmonic shaping while maintaining high-Q circular topology. However, the oscillator doesn't feature 3rd harmonic shaping and multi-mode operation, covering only an FTR of 17.6%.

This work presents a 135-GHz high-speed on–off keying (OOK) transmitter (TX) chip fabricated in 28-nm CMOS technology. A simplified 45-GHz Class-F voltage-controlled oscillator (VCO), with low-power consumption and implicit tripling characteristic, is proposed to generate a 135-GHz local oscillator (LO) signal. A Gilbert-cell modulator is utilized to support high-speed modulation and provide a high on/off ratio. Cascaded inverters are utilized to reshape the baseband signal distorted by external metal interconnects. Moreover, amplifiers based on neutralized $g_{m}$ core are used to boost the third harmonic signal at 135 GHz and amplify the D-band modulated signal. The TX was used to establish a wireless link via on-board Vivaldi antennas. Data rates of 29 and 30 Gb/s were achieved with an energy efficiency of 4.4 and 4.25 pJ/bit, respectively, over a 2-cm over-the-air (OTA) distance. In a low-loss channel such as bonding-wire connections, a data rate of 32 Gb/s with an energy efficiency of 2.68 pJ/b was achieved. PRBS31 was used to verify that the TX chip is suitable for applications requiring long pseudorandom binary sequence (PRBS) data streams. To the best of authors’ knowledge, this work achieves the highest error-free OTA data transmission rate among D-band OOK TX chips, providing a feasible CMOS solution for sub-terahertz (sub-THz) high-speed point-to-point wireless or wireline communication.

This paper presents a novel dual core voltage controlled oscillator utilizing inductive and capacitive coupling for 5G sub-6 GHz applications. For obtaining low phase noise, each core in the proposed dual core VCO consists of a transformer coupled Class-F topology where an auxiliary third harmonic resonance is provided by the LC tank in addition to fundamental resonance. A new method of inductive coupling between the transformer-based VCO cores has been proposed to increase the tuning range (TR). EM simulations in 65nm CMOS process show $\mathbf{4 3} \%$ of tuning range from 2.63 GHz to 4.07 GHz. Post layout EM simulations show phase noise of -114 dBc/Hz (100 kHz offset) and -134.2 dBc/Hz (1 MHz offset) at center frequency of 3.25 GHz. The VCO shows a FoMT of 204.48 dBc/Hz while consuming 18.37 mW of power from 0.5 V supply.

This paper presents the theory and implementation of a balanced dual-core inverse-class-F (class-F <inline-formula> <tex-math notation="LaTeX">$^{\mathrm{ -1}}$ </tex-math></inline-formula>) voltage-controlled oscillator (VCO). The class-F <inline-formula> <tex-math notation="LaTeX">$^{\mathrm{ -1}}$ </tex-math></inline-formula> topology supports high-quality-factor (high-<inline-formula> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula>) differential switched-capacitors (SCs) for both fundamental and 2 <inline-formula> <tex-math notation="LaTeX">$^{\mathrm{ nd}}$ </tex-math></inline-formula>-harmonic frequency tuning, which is beneficial for improving the phase noise (PN). However, the unequal parasitic capacitors from the NMOS and PMOS negative <inline-formula> <tex-math notation="LaTeX">${g}$ </tex-math></inline-formula> textsubscript m transistors make it impossible to minimize their flicker noise upconversions simultaneously, especially at high operating frequencies. The mechanism of this effect is analyzed qualitatively with the model of coupled oscillators and verified using the impulse-sensitivity function (ISF) approach. To address this issue, we propose a dual-core class-F <inline-formula> <tex-math notation="LaTeX">$^{\mathrm{ -1}}$ </tex-math></inline-formula> VCO that leverages a balanced coupling scheme to minimize the flicker noise upconversions of NMOS and PMOS transistors simultaneously and still keep the advantage of tuning the 2 <inline-formula> <tex-math notation="LaTeX">$^{\mathrm{ nd}}$ </tex-math></inline-formula>-harmonic frequency with differential SCs offered by the class-F <inline-formula> <tex-math notation="LaTeX">$^{\mathrm{ -1}}$ </tex-math></inline-formula> topology. Additionally, the symmetrical circuit topology aids in improving the differential output balancing. Prototyped in a 28-nm CMOS process without ultra-thick metal, the balanced dual-core class-F <inline-formula> <tex-math notation="LaTeX">$^{\mathrm{ -1}}$ </tex-math></inline-formula> VCO dissipates 19.7-mW and achieves a PN of <inline-formula> <tex-math notation="LaTeX">$\!-\!113.9/\!-\!135.8$ </tex-math></inline-formula>-dBc/Hz at 1/10-MHz offset from an 18.23-GHz carrier. Tuned from 15.22 to 18.23-GHz, the proposed VCO exhibits superior figure-of-merits (FoMs) at 1/10-MHz offset from 185.3/187.0 to 186.2/188.1-dBc/Hz.

This paper presents a low phase noise mmWave Class-F Voltage Controlled Oscillator (VCO) using a novel single-turn multi-tap (STMT) inductor. The proposed STMT based LC tank performs inductive division, thus achieving higher gate voltage swing. The proposed design operates as a Class-F oscillator with an auxiliary third harmonic impedance peak. Tail filtering has been used as a second harmonic trap. The VCO designed in 65 nm CMOS process operates from 24.8 to 28.97 GHz. The VCO shows phase noise of -84.87 dBc/Hz and -110 dBc/Hz at 100kHz and 1MHz offset respectively at 28.89 GHz and FoMT of 197 dBc/Hz at /MHz offset while consuming 4 mW of DC power for a tuning range of 15.51%.

This paper presents a CMOS circular-geometry quad-core voltage-controlled oscillator (VCO) with class-F operation and tail filtering to achieve ultra low phase noise in K band. The use of class-F operation in a circular-geometry multicore VCO further lowers phase noise but results in new mode ambiguity. We introduce cross-coupled narrow and thin metal traces in the class-F transformer secondary loop to suppress this new mode ambiguity. Also, we extend the circular geometry design to the VCO tail LC filters, reducing the chip area. A proof-of-concept prototype is fabricated in a standard 65 nm CMOS technology. In measurement, the VCO operates from 17.9 to 20.7 GHz. At 19 GHz, the VCO achieves a phase noise of -115 dBc/Hz at 1 MHz offset with a figure of merit (FoM) of -188.4 dBc/Hz.

In this paper, a Class-F voltage-controlled oscillator (VCO) with low-phase-noise (PN) and ultra-low-power consumption is proposed by reactivating the common-mode (CM) coupling factor in a 1:2 transformer. Unlike conventional designs that exclusively consider the differential-mode (DM) coupling factor in 1:2 transformers, our proposed architecture effectively leverages the combined potential of DM and CM coupling factors in a single transformer. For DM operation, a novel design method is presented to efficiently guide the design of ultra-low-power VCOs. This method provides clear insights into how Class-F3 resonator parameters influence the loop gain characteristics, establishing a quantitative framework for performance optimization. Regarding CM operation, the 1:2 transformer’s coupling mechanism is analyzed in detail for the first time. The analysis reveals that strategic layout optimization of the center tap can reactivate the CM coupling factor, effectively expanding the CM resonance to reduce PN. Furthermore, by incorporating a tightly coupled tertiary coil, a local oscillator signal with high spectral purity is realized. Fabricated in a 110-nm CMOS process, the proposed VCO achieves a 20.2% frequency tuning range (FTR) from 10.45 to 12.80 GHz, consuming 0.38-0.50 mW with 0.2-V power supply. The measured PN exhibits −107 and −130 dBc/Hz at 1 MHz and 10 MHz offset from a 12.80-GHz carrier, respectively, with corresponding excellent figures-of-merit (FoM) of 192 and 195 dBc/Hz, respectively.

This work presents a 28nm deeply power-scalable reconfigurable series-resonance/ClassF VCO with mutual-inductance self-cancellation and hybrid 8-shaped coupling techniques, achieving power scalability from 5.7 to 93.1 mW. By switching between parallel-resonance (Class-F) and series-resonance modes, the VCO achieves −149 dBc/Hz PN and 192.8 dBc/Hz FoM at a 10 MHz offset. This design enables flexible PN-power scalability for Wi-Fi 7, IoT, and wearable devices.

This paper presents a wideband, dual-core balanced inverse-class-F (class-F-1) VCO. The class-F-1 topology achieves a wideband impedance at the second harmonic frequency by constructing the proposed qual-coupled LC tanks, obtaining a 25.8% tuning range from 8.4-to-10.89 GHz. In addition, amplitude balancing is achieved by cross-linking the cores. Prototyped with 110-nm CMOS process, the VCO dissipates 20 mW with 1.2-V supply and achieves phase noise of -119 $I$ -139 dBc/Hz at 1- $I$ 10-MHz offset from 10-GHz carrier. The core area is 0.14 mm2.

This work presents a class-F voltage controlled oscillator (VCO) optimized for small area and low power. The VCO uses a transformer core to create an additional resonant peak at the third harmonic of the fundamental frequency and therefore improves phase noise performance. The transformer provides passive voltage gain which in turn allows for a reduction in supply voltage and power consumption. The VCO, with an area of only 0.022 mm2, was implemented in 22-nm fully depleted silicon on insulator (FDSOI) and achieves a peak area figure of merit $\text {FOM}_{A}=189~\text {dB}$ at 11.4 GHz. With a tuning range of 11.3–15.6 GHz, the peak power consumption is 6.6 mW at a supply voltage of 0.45 V.

This paper presents a differential inverse-class-F voltage-controlled-oscillator (VCO). By inversely coupling two identical inverse-class-F VCO through two coupling capacitors between the gates of the active devices, the proposed VCO can achieve differential output if the size of the coupling capacitors is selected properly, and therefore gets more suppression to the disturbance of the supply voltage. Meanwhile, the proposed VCO inherits the high FoM performance of the inverse-class-F topology and achieves phase noise improvement due to the electrical coupling. Designed and simulated in 28 nm CMOS process, the post-layout simulation shows that the prototype consumes 5.26 mW from a 0.7-V supply. The PN at 1 MHz offset is −121.4 dBc/Hz when oscillating at 7.92 GHz. The figure-of-merit (FoM) is about 192.2 dBc/Hz.

The rapid development of the next-generation high-speed wireless communication system has set increasingly stringent requirements on the spectral purity of local RF oscillators. Low phase noise is crucial to support advanced modulation scheme enabling high data-rates wireless link [1]. A viable popular approach is to coupled N identical oscillators together to improve the phase noise by 10log10 N at the cost of N times higher power [2]–[6]. Nevertheless, the coupling network needs to be designed carefully to avoid undesired multi-tone concurrent oscillations. Besides, area occupation is another issue of multi-core VCOs. The star-geometry as shown in Fig. 1. (bottom left), which is simple N times duplication of single core, occupies N times larger area so comes with an area penalty [3]–[5]. To solve this problem, circular geometry is proposed where the passives are merged into a single passive structure and the minimal realizable inductance is reduced while keeping a high Q factor [6]–[7]. In order to further reduce the silicon area, a square-geometry quad-core oscillator with inductor sharing technique is proposed in this paper and it exhibits a compact area of 0.09 mm2, which is the smallest quad-core VCO operating at a similar oscillation frequency. The unwanted mode is suppressed by the metal trace that connects the drain node of adjacent cores. Thanks to the proposed square-geometry and inductor sharing technique, the proposed quad-core class-F VCO can further reduce the area occupation. The proposed VCO is fabricated in 65nm CMOS technology. The measured phase noise is -137.2 dB/Hz at 10 MHz offset frequency from a carrier of 19 GHz, which translates to the FoM of 186.1 dBc/Hz.

The emerging wireless systems can profit from a low-phase-noise high-frequency-band local oscillator (LO) to enable the use of dense modulation schemes over a wide signal bandwidth. When the LO frequency escalates from RF to millimeter waves, the capacitive devices (e.g., varactor and switched capacitor) tend to dominate the tank quality factor (O) of the voltage-controlled oscillator (VCO), imposing a severe trade-off between the phase noise (PN) and the frequency tuning range. Meanwhile, the technology downscaling further exacerbates this trade-off since the advanced process nodes demand more metal layers to connect transistors in a higher density, diminishing the metal thickness and thus reducing the Q of the metal-oxide-metal (MOM) capacitor. Besides, the deteriorating 1/f noise of MOS transistors in the advanced processes is another challenge faced by the VCO PN performance. Consequently, the PNs and the figure-of-merits (FoMs) of recent VCOs in 28nm CMOS [1–3] are inferior to their 65nm [4] and 40nm [5] counterparts.

This paper presents a D-band Class-F harmonic voltage controlled oscillator (H-VCO) with a novel inductor-slot fusion tank, where the fundamental 35GHz signal and a considerably strong third harmonic at 105GHz are simultaneously excited. The desired 140GHz signal as forth order harmonic is self-mixed by an inherent up-mixer nearby tank and buffered to output through a two stage D-band buffer. A prototype is implemented and post-simulated upon commercial 65nm CMOS technology. EM simulation exhibits satisfying results with a tunning range of 32%, correspondingly 119-165GHz, within which the PN performance at 140GHz achieves -94.7dBc with 1MHz offset. The complete frequency generator draws 100mA current under 1V supply with a peak output power of -4 .6dBm. The figure-of-merit (FoM) remains between 176.4 and 178.2 dBc/Hz.

This work presents a 1.6 GHz to 2 GHz integer PLL with 2 MHz stepping, which is optimized for driving low-power 180 nm switched-capacitor (SC) circuits at a 1.2 V supply. To reduce the overall power consumption, a class-F VCO is implemented. Due to enriched odd harmonics of the oscillator, a rectangular oscillator signal is generated, which allows omitting output buffering stages. The rectangular signal results in a lowered power consumption and enables to directly drive SC-filters and an RF-divider using the oscillator signal. In addition, the proposed RF-divider includes a differential 4-phase signal generation at 868 MHz and 915 MHz SRD band frequencies that can be used for complex modulation schemes. With a fully integrated loop-filter, a maximum of integration is achieved. A test-chip was manufactured in a 1P6M 180 nm CMOS technology with triple-well option and confirms a PLL with a total active power consumption of 4.1 mW. It achieves a phase noise of -111 dBc/Hz at 1 MHz offset and a -42 dBc spurious response from a 1 MHz reference.

In this paper, the proposed millimeter-wave voltage controlled oscillator (VCO) is based on Class-F oscillator and adopts the design of multi-peak transformer to enhance the third harmonic so as to obtain higher frequency and lower phase noise. A high frequency millimeter wave VCO is realized by the design of a low frequency resonator. As a result, the VCO has lower phase noise and lower power consumption while obtaining wider frequency tuning range than traditional mm-Wave VCOs. In addition, a broadband buffer with a low-km transformer which can suppress the first-harmonic and extract the third-harmonic is proposed. Simulated results show that the proposed VCO exhibits phase noise of -93.6~-95.1dBc/Hz at 1 MHz offset at 72.8~90.1 GHz, and the DC power consumption of the VCO core is only 10.8mW at the supply voltage of 0.9V.

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In this paper, a new Class-F mode voltage-controlled oscillator (VCO) structure is presented. The VCO consists of two LC tanks to get two impedance peaks instead of using a transformer, which leads to a simpler design. The tuning range is from 5.49GHz to 6.19GHz and it consumes only 5.6mW with 0.8V power supply. The measured phase noise at 5.86GHz is -118dBc/Hz@ 1MHz and the figure of merit (FOM) is 186. The VCO is fabricated in 180-nm CMOS technology and occupies a die area of 0.78×0.86mm2.

A low phase noise, wideband Class-F voltage-controlled oscillator is proposed in this paper. A resonance at 3fLO is introduced for Class-F operation to reduce the phase noise. A 1:1 transformer is used in the proposed resonant tank rather than conventional 1:2 transformer. The capacitors in the layout are placed alternately to reduce the influence of parasitic inductances. The tail resistor array replaces the tail current source transistor in the proposed VCO for improving the phase noise performance. The proposed VCO is designed and implemented in 14nm FinFET CMOS process. The simulation results show that the operating frequency covers 17.6-22 GHz by 3-bit digital tuning. The Kvco is larger than 2GHz/V. The VCO achieves a phase noise of -106.8 dBc/Hz at 1 MHz offset frequency, and consumes 8.24 mW from a 0.8 V supply.

The demand for low-phase-noise and low-power-consumption voltage-controlled oscillators (VCOs) continues to grow, driven by the evolution of advanced applications such as 6G wireless communications and complex modulation schemes like 1024-QAM. Various techniques, including harmonic shaping and multi-core architectures, have been developed to simultaneously enhance phase noise performance and the figure-of-merit (FoM) of VCOs. However, a critical aspect often overlooked in the literature is the supply voltage. To achieve an optimal FoM, many designs employ reduced supply voltages, typically around half the standard value. While effective, integrating these designs into a complete system can be costly, as providing a unique reduced supply voltage externally is expensive. When using a non-standard supply voltage, VCOs face reliability issues unless components such as low-dropout regulators (LDOs), tail currents, or resistors are employed to control the voltage swing. These solutions, however, consume significant power-particularly when the core supply voltage is halved-and introduce noise into the VCO, thereby degrading the overall FoM. CMOS topology is another commonly used method to fit the standard supply voltage. However, the degraded performance of PMOS devices reduces the FoM in CMOS VCO. As shown in Fig. 1, a FoM gap of approximately 2 dB between standard and reduced supply voltage VCO is evident.

In this article, an enhanced class-F voltage-controlled oscillator (VCO) with common-mode-noise self-cancellation (CM-NC) and common-mode-noise isolation (CM-NI) technique is proposed. With the proposed CM-NC technique, the common-mode-noise current of the drain coil and that of the nearby source coil are in the opposite direction. Therefore, the magnetic fields generated by the two coils cancel each other, which reduces the noise injected into the VCO from power supply and the ground node. Moreover, the principle of decoupling between the two inductors is also employed to eliminate the influence of the common-mode tail inductor on the differential mode. By winding the gate coil into a double-turn structure, the coupling noise from the drain inductor to the gate is opposite to the induced current of the gate coil, thereby cutting off the noise coupling path from the drain to the gate. Thanks to the dual-core 8-shaped inductor structure, the phase noise (PN) is improved without increasing the area, compared with existing methods using separated and dedicated tail filtering inductors. The VCO is fabricated in a 65-nm complementary metal–oxide–semiconductor (CMOS) technology. The measured tuning range is 21.7% from 11.5 to 14.3 GHz. The PN and figure of merit (FoM) at 1-MHz offset are −119.2 and 192.8 dBc/Hz, respectively. The power consumption across the frequency tuning range is 5.6–10 mW. The core area is 0.065 mm2 and the total area is 0.26 mm2.

In this brief, the method of simultaneous frequency band and harmonic-mode switching is proposed to maintain broadband low phase noise (PN) performance in transformer-based harmonic-shaping voltage-controlled oscillators (VCOs). The switched-capacitor arrays used for frequency band switching are multiplexed to achieve harmonic-mode switching, which enables the current-reuse VCO to operate in class-<inline-formula> <tex-math notation="LaTeX">$\text{F}_{-1}$ </tex-math></inline-formula> and class-F3 modes at high- and low-band, respectively. Compared with manual harmonic tuning methods, the proposed method avoids the use of additional lossy harmonic tuning capacitors. The class-<inline-formula> <tex-math notation="LaTeX">$\text{F}_{-1/3}$ </tex-math></inline-formula> VCO is inherently area-efficient. The proposed VCO is fabricated in a 110-nm CMOS process. The measured frequency tuning range (FTR) is 6.18~9.33 GHz (40.6%). Thanks to dual-mode operation, the measured peak PN is −122.4 dBc/Hz at 1-MHz offset, and the FoM is 186.1~188.0 dB over the FTR. A −200.1 dB peak FoM with FTR (FoMT) is achieved.

A $17.9$-to-22.4GHz quad-core inverse-Class-F VCO achieving PN of −145.6 to $-141 \text{dBc} / \text{Hz}$ and an FoM of 194.3 to $196.9 \text{dBc} / \text{Hz}$ is reported. The VCO features a circular pentafilar transformer tank that provides high Q1/Q2 without requiring extra CM resonators. Multi-path synchronizations—in-phase at gates, out-of-phase at drains, and an auxiliary dual-path coil—equalize impedances at both $\mathrm{f}_{0}$ and $2 \mathrm{f}_{0}$. A segmented alignment technique is proposed to preserve 1D tuning with improved robustness against PVT variations.

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To address the complex nonlinear problem of determining class-F voltage-controlled oscillator (VCO) dimensions, this article introduces an electronic design automation (EDA) framework that rapidly optimizes multiple design objectives yielding superior outcomes. The framework incorporates fast frequency determination, harmonic alignment, and extremal optimization of multiobjective particle swarm optimization with crowding distance (FHE-MOPSO-CD), an efficient algorithm we developed specifically for class-F VCOs, which includes transformer-based tank circuit strategies and extremum optimization techniques. Using a 55-nm CMOS process, this algorithm optimized various class-F VCO topologies, achieving excellent metrics and confirming its versatility. Optimization results indicate that at a 10-MHz offset, the figure of merit (FoM) is at least 8.81 dBc/Hz higher than values reported in the literature. Compared with other analog/RF dimension optimization methods, our approach yielded a higher hypervolume, indicating better convergence and greater diversity of solutions.

Implementing dual-resonance class-F oscillators with transformer feedback beyond 60 GHz poses significant challenges due to the limited third-harmonic tank impedance when using small coils with low coupling factors. To address these limitations and leverage the phase noise advantages of class-F operation, this letter introduces a standing-wave oscillator (SWO) topology featuring an on-chip multiband transmission-line (t-line) resonator loaded with harmonically tuned open stubs. The proposed design enhances third-harmonic resonance while facilitating precise alignment of the oscillation frequencies. Three voltage-controlled oscillators (VCOs) were implemented using TSMC’s 65-nm LP technology, demonstrating that the proposed class-F half-wavelength SWO achieves phase noise improvements of 3.1 and 6.4 dB at a 1-MHz offset compared to conventional SWO and transformer-based class-F VCO, respectively.

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Emerging needs for incorporating multistandard or software-defined-radio transceivers onto a single chip necessitate oscillator signals with an octave coverage for enabling seamless full-range frequency synthesis. Although most current solutions, particularly in commercial products, rely on configurations that involve multiple oscillators, there is a strong demand for a single LC VCO that provides at least an octave frequency tuning range (FTR) and low phase noise (PN). Recent research has extensively explored multicore multimode operations to substantially extend the FTR of LC VCOs [1-5]. Among key benefits is the improvement in the PN due to the coupling of numerous identical VCO cores, though at the expense of power consumption. Additionally, any explicit loss from mode switching can be circumvented by effectively nullifying the currents flowing through the MOS switches. However, several unavoidable mechanisms can reduce the equivalent quality factor (Q), thus impacting the performance: (1) mismatch between different oscillation cores causes the tanks operation to deviate from their impedance peaks; (2) the use of destructive magnetic coupling in higher-frequency modes decreases the effective inductance, while losses remain nearly unchanged. Furthermore, due to the high complexity and increased constraints in these ultra-wideband VCO circuits, neither the impulse-sensitivity-function (ISF) reshaping based on multiresonance nor the drain-to-gate voltage-gain boosting for noise reduction of transistors have been implemented, as illustrated in Fig. 19.3.1 (top). Consequently, prior-art ultra-wideband VCOs exhibit figure-of-merits (FoMs) of approximately 5 to 10dB inferior to those found in their narrow-band counterparts.

This article presents the co-design of electromagnetic interference (EMI) shielding packaging and a W band VCO. The VCO employs a coupling co-existing tank that enables Class F operation and common mode expansion within a single core. The EMI-shielding packaging incorporates a ground layer to effectively shield EMI. A co-design approach is introduced to maintain the VCO's performance after packaging. Additionally, the packaging can be utilized to compensate for process corner variations. The article details the design and packaging process of the VCO. Fabricated in 65 nm CMOS technology, the VCO achieves a phase noise of −101.6 dBc/Hz @ 1 MHz at 81 GHz.

This paper presents a complementary-NMOS-PMOS (CMOS) dual-core inter-core-shaping class- ${F}_{23}$ voltage controlled oscillator (VCO) with low phase noise and high figure-of-merit (FoM). In contrast to the traditional class- ${F}_{23}$ VCO employing single-ended capacitors in the common-mode (CM), a CM excitation is introduced between CMOS transistor pairs with high-Q differential capacitors, thereby suppressing flicker noise up-conversion and improving phase noise performance. Moreover, a circular-geometry quad-coil transformer is designed to control the $3^{\text {rd }}$ harmonic in the differential mode (DM) for the waveform shaping, and counteract the magnetic flux between the inner and outer coils in CM, which eliminates parasitic effects on the $2^{\text {nd }}$ harmonic resonance. Fabricated in a 65-nm CMOS process, the dual-core $F_{23}$ VCO could cover a 17.5% frequency tuning range from 9.9 to 11.8 GHz. Consuming 12.7 mW from a 1.2 V voltage supply, the $1 / \mathbf{f}^{3}$ corner is about 240 kHz and a phase noise ranging from -118.7 to $-121.5 \mathrm{dBc} / \mathrm{Hz} {\text {@}} 1 \mathrm{MHz}$ offset is achieved, resulting in a FoM of $\mathbf{- 1 9 0. 4 d B c} {\text {@}} 1 M H z$ offset.

Series resonant voltage‐controlled oscillator (SR‐VCO) provides an effective solution for achieving ultralow noise due to their larger voltage swing. To further reduce the phase noise, a class‐F SR‐VCO architecture is proposed in this paper. By introducing a zero at the third harmonic of the resonant frequency, a drain current comprising fundamental and third harmonic components is generated, resulting in a pseudo‐square wave current waveform. This significantly reduces the effective pulse sensitivity function (ISF) of the VCO, leading to an improved noise figure. The paper details the design methodology for the class‐F SR‐VCO and validates it at 2.71‐ to 2.93‐GHz frequency band. Implemented with SMIC180‐nanometer standard CMOS, the VCO demonstrates an average phase noise of 139.9 dBc/Hz and a figure of merit (FOM) of 186.7 dB at 1‐MHz offset. The designed class‐F SR‐VCO consumes 119.5‐mA current from a 1.2‐V power supply.

This paper presents a class-F23 voltage-controlled oscillator (VCO) to improve the phase noise performance without manual $2^{\mathrm{n}\mathrm{d}_{-}}$ or $3^{\mathrm{r}\mathrm{d}}-$harmonic tuning. By leveraging a three-coil transformer, a differential-mode (DM) resonance expansion at $3^{\mathrm{r}\mathrm{d}}-$harmonic frequency is achieved while maintaining the class-F operation. Meanwhile, by utilizing a two-coil transformer-based resonator for the tail filtering, a wideband common-mode (CM) resonance at $2^{\mathrm{n}\mathrm{d}}-$harmonic frequency is realized. Prototyped in 65-nm CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 18.5 to 22.4 GHz with 1-MHz offset phase noise from -110.7 to -106.1 dBc/Hz, while consuming 5 mW at 0.5 V. The figure-of-merit (FoM) is 189.1 dBc/Hz, and the chip area is 0.061 m$\mathrm{m}^{2}$.

This paper details the theory and implementation of an inverse-class-F (class-<inline-formula> <tex-math notation="LaTeX">$\text{F}^{-1}$ </tex-math></inline-formula>) CMOS oscillator. It features: 1) a single-ended PMOS-NMOS-complementary architecture to generate the differential outputs and 2) a transformer-based two-port resonator to boost the drain-to-gate voltage gain (<inline-formula> <tex-math notation="LaTeX">$A_{\mathrm {V}}$ </tex-math></inline-formula>) while creating two intrinsic-high-<inline-formula> <tex-math notation="LaTeX">${Q}$ </tex-math></inline-formula> impedance peaks at the fundamental (<inline-formula> <tex-math notation="LaTeX">$f_{\mathrm {LO}}$ </tex-math></inline-formula>) and double (2<inline-formula> <tex-math notation="LaTeX">$f_{\mathrm {LO}}$ </tex-math></inline-formula>) oscillation frequencies. The enlarged second harmonic voltage extends the flat span in which the impulse sensitivity function (ISF) is minimum, and the amplified gate voltage swing reduces the current commutation time, thereby lowering the –<inline-formula> <tex-math notation="LaTeX">$g_{\mathrm {m}}$ </tex-math></inline-formula> transistor’s noise-to-phase noise (PN) conversion. Prototyped in 65-nm CMOS, the class-<inline-formula> <tex-math notation="LaTeX">$\text{F}^{-1}$ </tex-math></inline-formula> oscillator at 4 GHz exhibits a PN of −144.8 dBc/Hz at a 10-MHz offset, while offering a tuning range of 3.5–4.5 GHz. The corresponding figure of merit (FoM) is 196.1 dBc/Hz, and the die area is 0.14 mm².

No abstract available

No abstract available

This paper presents a class-F23 voltage-controlled oscillator (VCO) designed to improve phase noise performance through harmonic shaping while suppressing the flicker and white noise upconversion without manual 2nd or 3rd harmonic tuning. By leveraging a three-coil transformer-based resonator, the design achieves differential-mode (DM) resonance expansion at the 3rd harmonic frequency while maintaining the class-F operation. This approach eliminates the need for a low-quality (Q) factor switched-capacitor array (SCA) for 1st-to-3rd harmonic alignment, thereby improving the tank’s Q. Additionally, a two-coil transformer-based resonator is employed for tail filtering, enabling wideband common-mode (CM) resonance at the 2nd harmonic frequency, which helps to nullify flicker noise and prevent tank Q degradation due to the differential pair operating in the triode region. Implemented in a 65-nm CMOS process, the proposed prototype achieves a frequency tuning range from 18.5 to 22.4 GHz, phase noise from −110.7 to −106.1 dBc/Hz at 1-MHz offset, while consuming 5 mW and occupying a compact core area of 0.061 mm2, corresponding to a peak figure-of-merit (FoM) of 189.1 dBc/Hz and FoMT of 194.7 dBc/Hz.

A 6.27 GHz energy-efficient noise filtering class-F oscillator is designed in a 22 nm SOI CMOS process. A transformer-based resonator is adopted boosting the third harmonic of the fundamental wave and expanding phase insensitivity region in one oscillation period. The noise filter comprised of an inductor and a capacitor is used to reduce both the Q factor degradation of the resonator and the 1/f noise upconversion at the same time. Post-layout simulation results considering accurate 3D models for all relevant components proof an excellent phase noise of -127.5 dBc/Hz at 1 MHz offset drawing only 5.0 mW power consumption from a 0.8 V supply resulting in a figure of merit (FoM) of 196.4 dB.

This paper presents an ultra-lower-power (ULP) digital-to-time-converter (DTC)-assisted fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed hybrid time-to-digital converter (TDC) extends the vernier-TDC input range with little power overhead in order to overcome the stability issue in the conventional architectures. The hybrid TDC also facilitates a background gain calibration to achieve a stable in-band phase noise insensitive to process, voltage, and temperature (PVT) variations. The implementation of a buffer-cascaded DTC simplifies the design complexity of the fractional-N operation. The ADPLL also features a 200<inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> low-phase-noise inverse-class-F (class-F⁻¹) digitally controlled oscillator (DCO) without the need of two-dimensional (2-D) capacitor tuning for frequency alignment of the fundamental and 2^nd-harmonic. Fabricated in 65-nm CMOS, the ULP ADPLL prototype achieves 868fs_rms jitter in a fractional-N channel when consuming only 529<inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula>, corresponding to a figure-of-merit (FoM) of −244dB.

No abstract available

This paper presents a 142-154 GHz third-harmonic extracted Class-F oscillator featuring an FoM of -177.1 at 1-MHz offset. In this work, a magnetically coupled dual-core topology is applied to enhance the third harmonic for Class-F operation, which also effectively boosts the negative conductance of the oscillator. The boosted negative conductance relaxes the startup condition in the Colpitts oscillator and improves its phase noise. This oscillator is fabricated in a 22-nm CMOS FDSOI. At 154.5 GHz, the measured PN is -87.4 dBc/Hz at 1-MHz offset, and -101.8 dBc/Hz at 10 MHz offset.

No abstract available

In this article, we present a low phase noise (PN) mm-wave quadrature digitally controlled oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A third transformer coil is added for the inter-core coupling with the source terminals of the switching transistors. We identify that the inter-core coupling in quadrature oscillators causes an asymmetric flicker noise current, thus degrading flicker PN. As a remedy, we propose a deliberate drain-to-gate phase shift of the switching transistors by means of capacitive loading to fix this asymmetry. The ±90° I/Q mode ambiguity is also resolved by introducing another phase shift in the source-coupling; it is explained by a simplified analysis with phasor diagrams. Fabricated in the TSMC 28-nm LP CMOS, the prototype achieves PN of −112 dBc/Hz and figure-of-merit (FoM) of −185 dB at 1-MHz offset of 25.7 GHz. The measured flicker PN corner is 140–250 kHz and image rejection ratio (IRR) >47 dB over the whole 18% tuning range (TR). To the best of the authors’ knowledge, it is the best reported PN and IRR for a mm-wave quadrature oscillator.

This paper presents a millimeter-wave (mmW) frequency generation stage aimed at minimizing phase noise (PN) via waveform shaping and harmonic extraction while suppressing flicker noise upconversion via proper harmonic terminations. A 2nd-harmonic resonance is assisted by a proposed embedded decoupling capacitor inside a transformer for explicit common-mode current return path. Class-F operation with 3rd-harmonic boosting and extraction techniques allow maintaining high quality factor of a 10-GHz tank at the 30-GHz frequency generation. We further propose a comprehensive quantitative analysis method of flicker noise upconversion mechanism exploiting latest insights into the flicker noise mechanisms in nanoscale short-channel transistors, and it is numerically verified against foundry models. The proposed 27.3- to 31.2-GHz oscillator is implemented in TSMC 28-nm CMOS. It achieves PN of −106 dBc/Hz at 1-MHz offset and figure-of-merit (FoM) of −184 dBc/Hz at 27.3 GHz. Its flicker phase-noise ( $1/f^{3}$ ) corner of 120 kHz is an order-of-magnitude better than currently achievable at mmW.

This paper presents a mmW frequency generation stage aimed at minimizing phase noise via waveform shaping and harmonic extraction while suppressing flicker noise upconversion via proper harmonic terminations. A second-harmonic tank resonance is assisted by a proposed embedded decoupling capacitor inside a transformer for shortest and well controlled common-mode current return path. Class-F operation with third-harmonic boosting and extraction techniques allow maintaining high quality factor of a 10 GHz tank at the 30 GHz frequency generation while providing implicit divide-by-3 functionality. The proposed 27.3–31.2 GHz oscillator is implemented in 28-nm CMOS. It achieves phase noise of −106 dBc/Hz at 1-MHz offset and figure-of-merit (FoM) of −184 dB at 27.3GHz. Its flicker phase-noise (1/f3) corner of 120 kHz is an order-of-magnitude better than currently achievable at mmW.

No abstract available

In this study, a novel resonator is proposed to be connected to a differential complementary metal‐oxide semiconductor (CMOS) or bipolar junction transistor (BJT) circuit to form an oscillator operating as a class‐F oscillator. Currently, there are only two resonators as alternatives to be reported and proposed for class‐F oscillators. The first one is the transformer‐coupled resonator, and the second one is the two‐separate‐tank resonator. The objective of this study is to present a novel resonator providing class‐F oscillation with lower phase noise as well as higher figure of merit (FoM) compared with the two available alternatives. Theoretical basis of the proposed resonator is first presented and formulated. To compare the performance of the proposed resonator with that of the two available alternatives, the three resonators are implemented in standard 180‐nm CMOS technology. Measured results demonstrate that the phase noise of the proposed resonator is −148.19 dBc/Hz which is lower than that of the transformer‐coupled resonator (−147.73 dBc/Hz) and two‐separate‐tank resonator (−142.84 dBc/Hz). Also, the FoM of the proposed resonator is 187.17 dB which is higher than that of the two alternatives (185.23 and 183.39 dB). These points clearly prove the novelty and contribution of this work in presenting a novel resonator with better performance compared with the two available alternatives.

A novel complementary ClassF 23 voltage‐controlled oscillator (VCO) is proposed. The design employs a transformer‐based tank and integrates two additional LC tanks that provide resonance at the third harmonic frequency. This harmonic superposition enables a sharp zero‐crossing region, which minimizes the effective Impulse Sensitivity Function (ISF), and consequently further improves phase noise (PN). Simulation results show that the additional third harmonic resonance contributes to a 1.4 dB reduction in phase noise compared with a standard Class F −1 oscillator. Fabricated in a 180 nm CMOS process, the prototype VCO occupies an area of 0.88 × 1 mm 2 . Measurement results show a tuning range of 4.26–4.58 GHz. The PN at 1 MHz offset is −126 dBc/Hz from the 4.26 GHz carrier frequency, with an average PN better than −120 dBc/Hz across the entire tuning range. A figure‐of‐merit (FoM) of 190.6 dBc/Hz is obtained at the 1 MHz offset. Under a 1.8 V supply voltage, the proposed design consumes a power of 6.2 mW.

The 1/f (flicker) noise upconversion degrades the close-in spectrum of CMOS RF oscillators. The resulting 1/f3 phase noise (PN) can be an issue in PLLs with a loop bandwidth of <;1MHz, which practically implies all cellular phones. A previously published noise-filtering technique [1] and adding resistors in series with gm-device drains [2] have shown significant reduction of the 1/f3 oscillator PN corner. However, the former needs an additional tunable inductor and the latter degrades PN in the 20dB/dec region.

No abstract available

This paper presents a low noise self-mixing voltage-controlled oscillator. The proposed VCO consists of coupled fundamental oscillators and two self-mixing triplers. In order to reduce the flicker noise and improve the phase noise (PN) performance, a Class-F2technique is adopted in the proposed fundamental oscillator design. Meanwhile, the PN is further reduced by 3 dB with the use of a coupling technology. In addition, by using the transformer-based tank, the self-mixing tripler can operate from 22.2 to 26.4 GHz with sufficient output power. The proposed VCO is designed and simulated utilizing 65 nm CMOS process. The post-layout simulation shows the PN is −113.6 dBc/Hz at 1 MHz offset from 24.28 GHz, and the Figure of merit (FOM) is about 187.5 dBc/Hz while consuming 23.7 mW from a 1-V supply.

We introduce a new mode of oscillation in an LC-tank: an inverse class-F23. In contrast to the conventional class-F oscillators, in which a high value of the real impedance (i.e., resistance) is presented to the third (in class-F3) or/and to the second (in class-F2/class-F23) oscillator harmonics via an auxiliary resonance, here low resistive impedances (resembling a non-ideal short) are presented at both the second and third harmonics. This is made possible by tight magnetic coupling in the differential and common modes, respectively, afforded by a new compact 2:3 transformer. Being largely free from the harmonics in the voltage waveform and their possible deleterious phase shift effects on the flicker noise up-conversion, the phase noise performance in the flicker and thermal regions is further improved by narrowing the conduction angle. The 2:3 step-up transformer also provides a high passive gain to help with the startup in face of low supply. The switched-capacitor banks and cross-coupled transistor pair are carefully integrated under the transformer with a special arrangement of native (high-resistivity) substrate layer to mitigate their effect on the oscillation while reducing the area by 30%. The proposed digitally controlled oscillator (DCO) is implemented in 28-nm CMOS and achieves −95 dBc/Hz and −118 dBc/Hz at 100 kHz and 1 MHz offsets, respectively, while operating at a 0.3 V supply. The measured $1/f^{3}$ corner stays within 60 to 100 kHz over the 35% tuning range (TR) (from 2.02 to 2.87 GHz). This results in a figure-of-merit (FoM) with normalized TR (FoMT) of −196 and −199 dB at 100 kHz and 1 MHz offsets, respectively, is a record in the space of ≤0.5 V and ≤1 mW.

This article presents a low-jitter sub-sampling chopper phase-locked loop (SS-CPLL) that incorporates a novel chopping charge pump (C-CP) to mitigate 1/f noise in short-channel devices operating at a low supply voltage of 0.75 V. A charge-share cancellation technique is introduced to suppress ripple generated by residual charge from the previous reference period. The chopping modulation further reduces the charge pump’s white noise by filtering out high-order harmonics of folded noise, thereby significantly lowering in-band noise. In addition, a high-swing class-C/F2 voltage-controlled oscillator (VCO) is proposed to optimize out-of-band noise while maintaining low power consumption. Fabricated in 65-nm complementary metal oxide semiconductor (CMOS) with a core area of 0.64 mm2, the SS-CPLL achieves an in-band phase noise of −111.9 dBc/Hz at 1-kHz offset, an integrated jitter of 49.9 fs, and a figure-of-merit (FoM) of −257.1 dB at 9 GHz, while consuming 7.8 mW of power. The proposed SS-CPLL reduces in-band noise by approximately 15 dB compared with a conventional sub-sampling phase-locked loop (SSPLL), while maintaining a similar reference spur level of −58 dBc/Hz. This highlights the effectiveness of the C-CP and charge-share cancellation techniques.

This paper presents the design of the Charge Sampling Phase-Locked Loop working on 11 GHz with rms jitter less than 100 fs. The presented PLL works with the 100 MHz reference source and its main advantage is a phase detector PD, working in charge domain, allowing to minimize power consumption while simultaneously keeping the high gain of the phase difference. To alleviate spur transfer from periodic phase detector to PLL high common mode rejection ratio, CMRR operational transconductance amplifier OTA is used with Common Mode CM amplifier, which tune OTA output level improving frequency range. In addition, the differential input class D/F2 Voltage Controlled Oscillator VCO with one inductor turn is used. The proposed circuit is designed in the CMOS 40 nm process, is supplied from two supply sources 1.1 V and 0.6 V and consumes about 5 mW of power.

This paper presents a comprehensive study of phase noise (PN) suppression in LC‐tank oscillators. The goal of this study is to provide designers with the latest techniques for reducing PN in cross‐coupled oscillators. To this end, we begin with a discussion of two prevalent PN models in oscillators: Hajimiri and Demir. We prefer the Hajimiri model because it does not involve very complicated math, and it offers engineers better insight into designing low‐PN oscillators in the two‐PN close‐in regions in an oscillator spectrum (1/f2 and 1/f3). In 1/f2 region, we show that a need for a large output‐voltage swing leads to Class D and B oscillators, and a large output‐current swing results in Class C oscillators. Also, reduction of the impulse sensitivity functions (ISFs) of an oscillator core can happen in Class F oscillators. A few solutions are presented for mitigating flicker noise up‐conversion, such as adding resistances, controlling the oscillation amplitude, decreasing the conduction angle, guiding the high‐frequency harmonics of current, and shifting the phase of VGS against VDS. We also provide a comparison of recent state‐of‐the‐art literature to show what constitutes a good PN in both 1/f2 and 1/f3 regions in cross‐coupled oscillators. We conclude that a cross‐coupled oscillator can reach the best performances in 1/f3 and 1/f2 PN regions if the oscillator is designed in Class C with the K block and uses the techniques of narrowing the conduction angle, the tail inductor, and the modified tank simultaneously.

No abstract available

No abstract available

Rapid development of wireless communication technology makes low phase-noise (PN) millimeter-wave (mm-wave) oscillators increasingly critical. However, the increasing operation frequency shrinks the physical dimensions of inductors, leading to a destructive coupling among the peripheral edges of the inductors. This inevitably degrades the quality factor (Q-factor) of the resonant tank, thereby deteriorating the PN (Fig. 34.5.1 (top left)) [1]. Coupling multiple oscillators is an effective strategy for optimizing PN (Fig. 34.5.1 (top right)) at mm-wave frequencies. An N-core coupled oscillator theoretically can reduce the PN by $10\log_{10}(\mathrm{N})$. Figure 34.5.1 (bottom left) shows a star-connected quad-core voltage-controlled oscillator (VCO) that utilizes four individual spiral inductors [2]. However, it suffers from the Q-factor degradation in each inductor at mm-wave frequencies and noise upconversion to PN because of the absence of additional harmonic shaping. [3] presented a circular-connected quad-core VCO to overcome the Q-factor limitation of small-radius inductors due to destructive coupling (Fig. 34.5.1 (bottom middle)), since the circular-connected coil can achieve a high Q-factor with ultra-low inductance. Furthermore, a circular transformer-based resonant tank is designed to provide the $2\text{nd}$ -harmonic shaping. However, the design fails to maintain an optimal PN performance, particularly the $1/\mathrm{f}^{3}$ PN corner, across a wide frequency tuning range (FTR) due to its inability to align harmonic impedance peaks, which is essential in mm-wave VCOs. In mm-wave phase-locked loops (PLLs), the increasing frequency-division ratio necessitates a narrow loop bandwidth to mitigate the in-band PN introduced by the reference signal [4]. When a VCO exhibits a high $1/\mathrm{f}^{3}$ PN corner, out-of-band PN, dominated by the VCO, greatly degrades the PLL jitter performance, resulting in limited achievable data-rates in mm-wave transceivers. To realize the manual alignment of the 1st-to-2nd and 1st-to-3rd harmonic resonant frequencies, supplementary switched-capacitor arrays (SCAs) or varactors are needed. However, they cause severe Q-factor degradation in the mm-wave band and eventually worsen the PN performance.

Low-cost high-efficiency BLE transmitters (TXs) are highly demanded for short-range wireless connectivity. The system efficiency of previous BLE TXs is mainly limited by PLL and PA performance to satisfy BLE requirements [1]–[3]. In this work, a 0.6 V fully-integrated BLE TX shown in Fig. 1 is proposed to achieve 25% system efficiency at 0 dBm output with following features: (1) a submW RDAC-based hybrid PLL [4] with common-mode (CM) ripple cancellation to reduce reference spur; (2) a switching current-source (SCS) D/VCO with a step-up transformer and a shared bias resistor for differential varactors to improve efficiency and phase noise; (3) a duty-cycle controlled class-E/F2 digital PA to suppress $3^{\text {rd }}$-harmonic distortion $\left(\mathrm{HD}_{3}\right)$ without degrading PA efficiency; (4) a calibration-free 1-bit $\Delta \Sigma$ high-pass modulation with FIR filtering to overcome the nonlinearity issue of a low-voltage DCO in two-point modulation [5].

Class-E/F₃ power amplifier (PA) is a hybrid switching PA that enhances the performance of Class-E PA by reducing its peak switch voltage. The output power and the efficiency of a Class-E/F₃ PA are sensitive to the values of the load network components. To minimize this issue, we propose a Class-E/F₃ power oscillator (PO) whose feedback network is composed of a low-Q <italic>RC</italic> circuit. In the proposed circuit, the switching frequency of the PO is defined by the resonance frequencies of the load network, and as such, the PO remains fairly tuned, even if the load network components vary considerably. As a result, the output power and the efficiency of the proposed PO show negligible sensitivities to the changes in the component values. Additionally, we present a design procedure for the proposed PO. To verify the circuit operation and the design procedure, a prototype circuit was designed and implemented. At <inline-formula><tex-math notation="LaTeX">${{V}_{\text{DD}}} = \ \text{4.5}{\rm{\ V}}$</tex-math></inline-formula>, the measured output power, the efficiency, and the switching frequency of the prototype PO are <inline-formula><tex-math notation="LaTeX">$\text{1.023}\ \mathrm{W}$</tex-math></inline-formula>, 93.5%, and <inline-formula><tex-math notation="LaTeX">$\text{800}\ \text{kHz},$</tex-math></inline-formula> respectively. Simulation and measurement results confirm that the output power and the efficiency of the proposed PO have negligible sensitivities to the variations in the component values.

In this paper, a three-winding transformer-based Class-F23 Quad-Core VCO is proposed. By using a three-winding transformer, the common-mode (CM) resonances around the second harmonic and the differential-mode (DM) resonances around the third harmonic are extended while maintaining the operation of Class- F23 VCO. Fabricated in a 28-nm CMOS process, the continuous tuning range of the proposed VCO is 39.4%, from 5.5 to 8.2 GHz. The minimum phase noise is −135.1 dBc/Hz at the 1MHz offset of 5.5GHz, corresponding to the VCO figure of merit (FoM) of 191.1 dBc/Hz. The 1/f3 phase noise corner is 180 to 230 kHz over the tuning range.